Make sure that you always end the last line by pressing Enter. This adds a new line character to the line, and informs the simulator that the voltage definition is complete. If you do not do this, you will likely get a netlist read error when you try to Netlist and Run the simulation. Save the text file. You can exit the text editor.
However, you may want to keep the editor open to work on other simulation stimulus files later. If you have any trouble creating your own stimulus file, you can download a file with the same values as above from the class website.
Choose Lab1A. Regarding the Stimulus File The voltage sources above are defined using spectre syntax. Although you can vary the timing values as necessary to meet simulation goals, the rise and fall times shown in Step 6 are good for the chosen CMOS technology and should not be modified unless you are sure you know what you are doing. The illustration below helps to define the pulse waveform parameters.
Illustration of pulse waveform parameters left and two example pulse definitions right Cadence Virtuoso Logic Gates Tutorial rev: p. Once you have saved the stimulus file, return to the ADE window and link your stimulus file to the simulation program.
In the setup window that opens, you need to locate your stimulus file. Click the Browse button, select your stimulus file from the window that opens, and click Open to return to the setup window. If so, click OK to close the setup window without changing anything else. Simulation Files Setup window Setup Output Traces: The only step that remains before running the simulation is to select what signals you would like to view after the simulation is complete.
Then, select click on the wires connected to each of the inputs A and B. As you click, you should see the signals being added to the ADE window.
This completes your simulation setup. Your ADE window should now look like the image on the right. Running Functional Simulations transient analysis Now you will verify that the circuit you designed is indeed operating like and AND gate. Running the Simulation: 1. When the simulation is complete, the VCL log should show "reading simulation data The simulation results will be plotted in a waveform window. Initially, all plotted signals will appear on top of each other.
Under Part 1 of the Lab 1 Check-off Sheet, enter the expected output values 0 or 1 in the Theoretical column for each input combination of an AND gate. Now, view the plotted signals in the waveform window. Observe the output value 0 or 1 for each A,B input combination 0, 0 , etc. Note: the inputs will not be in the save order as the truth table. If not, look back at your circuit schematic and try to determine what is wrong.
Re-run simulations until you get the proper response. Consult the TA if you need help. Simulation waveform window with slightly different stimulus pattern than defined above 5. When your AND gate is simulating correctly, show the TA your schematic, symbol, and simulation results. To close all Virtuoso windows, it is best to close them individually to ensure everything has been saved.
You have now completed the tutorial and can continue with the next step of your lab assignment. Please note, the following appendix provides valuable information regarding saving images of schematics, simulation plots, etc.
You will need to perform this task later. You can either try it now for practice or refer to this tutorial in later labs when these steps are required. A second appendix provides instruction on saving and loading simulation states that might save you some time in the future. Just remember that this information is in this tutorial.
The options in the Trace Attributes window are shown below and are self explanatory. Try changing all traces to Solid and Bold style. Adjusting waveform display parameters In order to save a graph or schematic as an image file, for example to include within a report, follow the steps below. The image file will be saved in your current working directory from which you initially launched Virtuoso unless you browse to a new location.
The configuration window to the right will open. Enter in the name at the top of the window, select the image type PNG by default and select the Background to be Transparent generally preferred over a black background. Click Export and the image will be saved in your virtuoso working directory.
However, the default settings can consume a lot of disc space so be sure you study your options a bit and monitor your disc usage if you choose to use this feature. Thus, you can use the same Save As name for multiple cells without overwriting each other. Saving outputs from complex cells with multiple plotted node waveforms can generate very large GB! This window can be opened by simply pressing the I key on the keyboard as well. Select the nm technology library gpdk as the Library.
When a cell, such as nmos, is selected, the symbol view has to be chosen. When a cell and its view is selected, the Add Instance window comes up showing the selected cell and view for it, as shown below.
Gate-width W , Gate-length L and Finger-width dimension of unit transistor can be specified. For now, let us keep the default dimensions. Press Hide on the Add Instance window. Place the cell nmos and press Escape button on the keyboard. Press F to fit the design to the screen Zoom to Fit.
From now on gpdk library would be chosen by default. Select the symbol view of pmos cell. Place the cell pmos and press Escape button on the keyboard. To zoom —in and zoom-out, keep CTRL button pressed and use the mouse scroll-button.
You can press F to fit the schematic to the screen. Special Keys Press W to draw narrow wire. To finish wiring, stop moving the keyboard and press ESC button. Press Create-Pins or the its shortcut or press P. Special Keys Press P to add Pins. Set the direction of Vin and Vout as input and output, respectively. Save your schematic. To do this, press Setup--Stimuli. One Apply is pressed, stimulus state say 0V , type dc and that it is enabled ON would be displayed in the window.
The features of this pulse should be the following. This can be set after pressing Analysis- Choose. To choose transient analysis, choose tran for dc analysis, choose dc.
Ensure that Accuracy Defaults is set to moderate and Enabled is selected. Press Apply or Ok. To learn more, view our Privacy Policy. Log In Sign Up. Download Free PDF. Destaw Masresha. Download PDF. A short summary of this paper. Open the terminal window. Now you should be able to run the Cadence tools. Never run Cadence from your root directory, it creates many extra files that will clutter your root. Instead please create a directory e.
Fill in the name of the new library e. It will open the Library Manager window Fig 4 as shown below. It is easier to work with Library Manager. However, for this document we will work through Virtuoso- CIW window. Let's start our first schematic now! Fill in the information in the dialogue window as below and then press OK.
Spend some time analyzing the window. On the left side you have various shortcuts to common used commands such as: placing component instances looks like an IC , drawing wires, placing ports, stretching, copying, zooming in and out, saving, etc.
If you pass the mouse pointer on top of the buttons you get short pop-up help messages. You also have access to these commands and others from the menu. It is not possible here to describe all the functionality of Virtuoso Schematic so you are strongly encouraged to read the on-line user manuals.
You should notice that the top bar of the window will display the name of the library CMOSInverter , cellview myinverter and schematic at the end.
Expand the Virtuoso Schematic Editing window if necessary. Follow the steps now.
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